RD RAM

Abstract

During the last two decades, there has been an exponential growth in the  operational speed of microprocessors. Also RAM capacities have been improving at more than fifty percent per year.  

Introduction

One of the constants in computer technology is the continuing advancement in operational speed. A few years ago, a 66 MHz PC was considered “lightning fast”. Today’s common desktop machine operates at many times that frequency.This technology is based on a very high-speed, chip-to-chip interface and has been incorporated into DRAM architectures called Rambus DRAM or RDRAM. It can also be used with conventional processors and controllers to achieve a performance rate that is 100 times faster than conventional DRAMs. At the heart of the Rambus Channel Memory architecture, is ordinary DRAM cells to store information.  

 Rambus Protocol

Packets

The transactions between the devices in the Channel are completely different from the existing RAMs. Data and commands are routed over the Rambus channel in packets. Each packet is 10 ns long (four 2.5-ns clock cycles) and contains eight items (data or commands). ROW packets consist of 24 bits (8 bursts of 3 bits); COLUMN packets are made up of 40 bits of information (8 bursts of 5 bits). DATA packets consist of 144 bits (8 bursts of 18 bits, including parity) that follow COLUMN packets for certain operations. ROW, COLUMN and DATA packets are largely independent; individual bus operations employ different combinations of theses packet types. 

Real World Performance: Latency

        Component latency is defined as the time between row strobe on the command pin and the delivery of the first bit of data on the output pin. Looking at the controller’s perspective, system latency is the total time from when a controller drives an address to when it samples the last of the read data. The latency of the memory core (t-RAC) is the largest contributor to component latency. Despite relatively slow memory offerings from memory vendors, (t-RAC = -45 ns for RDRAM memory, 39 ns for DDR and 226 ns for SDRAM) RDRAM maintains a very respectable system latency for transferring 16 and 32 bytes of data.

System Cost: I/Os And Support Components

Interface pincount translates directly into signals or that must be routed across motherboards, connectors and modules. SDRAM and DDR must deal with wide parallel buses that become unevenly loaded as the system capacity increases: every DRAM device must attach to the command bus, while only a portion of the data bus connects to each device. The resulting system may be required to deal with decreased signal integrity and smaller timing windows by using multiple address bus copies, 2 cycle addressing, extra system components or limitations on expansion to compensate for losses.